1. Field of the Invention
The present invention relates to a CMOS J-K flip-flop circuit built in, especially, an integrated circuit.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing the first arrangement of a conventional J-K flip-flop circuit. The output from a NOR gate 101 is connected to the NOR input of an AND.NOR composite gate 102, and the output from the composite gate 102 is connected to the input of a CMOS clocked inverter 103. The output from the clocked inverter 103 is connected to one latch node of a flip-flop 104 as a master flip-flop obtained by connecting the inputs and outputs of two inverters to each other. The other latch node of the flip-flop 104 is connected to the input of a CMOS clocked inverter 105. The output from the clocked inverter 105 is connected to an output BQ as one latch node of a flip-flop 106 which serves as a slave flip-flop obtained by connecting the inputs and outputs of two inverters to each other. The other latch node of the flip-flop 106 is an output Q, and becomes one input of the NOR gate 101 and one AND input of the composite gate 102. The other input of the NOR gate 101 is a J signal input, and the other AND input of the composite gate is a K signal input. The outputs of this circuit become outputs Q and BQ (inverted Q) of the flip-flop 107.
FIG. 2 is a circuit diagram showing the second arrangement of a conventional J-K flip-flop circuit. The outputs from 3-input NAND gates 111 and 112 are respectively connected to the reset and set inputs of a master R-S flip-flop constituted by NAND gates 113 and 114, and the outputs from this flip-flop are connected to one-inputs of NAND gates 115 and 116. The outputs from the NAND gates 115 and 116 are respectively connected to the reset and set inputs of a slave R-S flip-flop constituted by NAND gates 117 and 118. Outputs Q and BQ of this flip-flop become the circuit outputs. The output Q is connected to the first input of the NAND gate 112, and the output BQ is connected to the first input of the NAND gate 111. The second inputs of the NAND gates 111 and 112 are respectively J and K inputs, and their third inputs are inputs of a clock pulse .phi.1. A clock pulse .phi.2 is input to the other inputs of the NAND gates 115 and 116.
In each of the above-mentioned circuit arrangements, the J and K inputs are fetched by the master flip-flop by an inverter operation in response to the clock pulses CP and BCP (inverted CP) or a gate operation in response to the clock pulses .phi.1 and .phi.2, and are shifted to the slave flip-flop to obtain the outputs Q and BQ.
Problems of the above-mentioned circuits are as follows. As the first problem, since the circuit is constituted by a large number of transistors, it requires a large area when it is built in an LSI, resulting in a high-cost LSI. In the conventional circuit described above, P- and N-channel MOS transistors are complementarily built in, and their numbers are almost equal to each other. If a CMOS inverter constituted by two transistor elements is connected to one input line to a gate circuit, 26 transistors are required for constituting the circuit shown in FIG. 1, and 36 transistors are required for constituting the circuit shown in FIG. 2. When the ON resistances of the N- and P-channel MOS transistors are set to be equal to each other, since the mobility of the P-channel MOS transistor is smaller than that of the N-channel MOS transistor, a large size (channel width) must be allotted to the P-channel MOS transistor, resulting in an increase in area of the circuit.
As the second problem, each of the above-mentioned circuit is not suitable for a high-speed operation. Each of the above-mentioned circuit arrangements is designed, so that both the P- and N-channel MOS transistors have the same characteristics, thus attempting to achieve a high-speed operation. A high-speed operation is achieved by setting substantially the same channel lengths and threshold voltages of both the N- and P-channel MOS transistors. However, in practice, the manufacturing processes of P- and N-channel MOS transistors must include processes having different influences for MOS transistor operations, and it is difficult to set these influences (the channel lengths and threshold voltages of the N- and P-channel MOS transistors) to be equal to each other. Therefore, the above-mentioned circuits are not suitable for a high-speed operation.